Semiconductor memory devices are used extensively to store data. Static and Dynamic Random Access Memory (SRAM and DRAM) are widely used in many applications. SRAM typically consists of six transistors and hence has a large cell size. However, unlike DRAM, it does not require periodic refresh operation to maintain its memory state. Conventional DRAM cells consist of one-transistor and one-capacitor (1T/1C) structure. As the 1T/1C memory cell feature is being scaled, difficulties arise due to the necessity of maintaining the capacitance value. DRAM based on the electrically floating body effect has been proposed (see for example “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002). Such memory eliminates the capacitor used in conventional 1T/1C memory cell, and thus is easier to scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell.
There is a continuing need for semiconductor memory devices that are smaller in size than currently existing devices.
The present invention meets the above need and more.